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energy metering ic with integrated oscillator and reverse polarity indication ad71056 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features on-chip oscillator as clock source high accuracy, supports 50 hz/60 hz iec62053-21 less than 0.1% error over a dynamic range of 500 to 1 supplies average real power on frequency outputs (f1, f2) high frequency output (cf) calibrates and supplies instantaneous real power logic output (revp) indicates potential miswiring or negative power direct drive for electromechanical counters and 2-phase stepper motors (f1, f2) proprietary adcs and dsp provide high accuracy over large variations in environmental conditions and time on-chip power supply monitoring on-chip creep protection (no load threshold) on-chip reference 2.45 v (20 ppm/c typical) with external overdrive capability single 5 v supply, low power (20 mw typical) low cost cmos process general description the ad71056 1 is a high accuracy, electrical energy metering ic with a precise oscillator circuit that serves as a clock source to the chip. the ad71056 eliminates the need for an external crystal or resonator, thus reducing the overall cost of building a meter with this ic. the chip directly interfaces with the shunt resistor. the ad71056 specifications surpass the accuracy requirements as quoted in the iec62053-21 standard. the only analog circuitry used in the ad71056 is in the - adcs and reference circuit. all other signal processing, such as multiplication and filtering, is carried out in the digital domain. this approach provides superior stability and accuracy over time and in extreme environmental conditions. the ad71056 supplies average real power information on f1 and f2, the low frequency outputs. these outputs either directly drive an electromechanical counter or interface with an mcu. the high frequency cf logic output, ideal for calibration purposes, provides instantaneous real power information. the ad71056 includes a power supply monitoring circuit on the v dd supply pin. the ad71056 remains inactive until the supply voltage on v dd reaches approximately 4 v. if the supply falls below 4 v, the ad71056 also remains inactive and the f1, f2, and cf outputs are in their nonactive modes. internal phase matching circuitry ensures that the voltage and current channels are phase matched, and the hpf in the current channel eliminates dc offsets. an internal no load threshold ensures that the ad71056 does not exhibit creep when no load is present. the part is available in a 16-lead, narrow body soic package. functional block diagram multiplier revp v2p v2n v1p rclkin ref in/out f1 f2 cf scf s0 s1 phase correction 4k ? ...110101... signal processing block power supply monitor - adc v1n ad71056 ...11011001... 2.5v reference v dd agnd dgnd internal oscillator - adc lpf hpf + + 1 6 13 7 11 8 10 12 14 16 15 9 digital-to-frequency converter 2 3 4 5 05636-001 figure 1. 1 u.s. patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.
ad71056 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 general d escription ......................................................................... 1 functional b lock d iagram .............................................................. 1 revision h istory ............................................................................... 2 specifications..................................................................................... 3 timing c haracteristics ................................................................ 4 absolute m aximum r atings............................................................ 5 esd c aution.................................................................................. 5 terminology ...................................................................................... 6 pin c onfiguration a nd f unction d escriptions............................. 7 typical p erformance c haracteristics ............................................. 8 theory o f o peration ...................................................................... 10 power f actor c onsiderations.................................................... 10 nonsinusoidal v oltage a nd c urrent........................................ 10 applications..................................................................................... 12 analog i nputs ............................................................................. 12 power s upply m onitor............................................................... 13 internal o scillator ( osc).......................................................... 15 transfer f unction....................................................................... 15 selecting a f requency f or a n e nergy m eter a pplication...... 16 no l oad t hreshold .................................................................... 17 negative p ower i nformation..................................................... 17 outline d imensions ....................................................................... 18 ordering g uide .......................................................................... 18 revision history 8/06revision a: initial version
ad71056 rev. a | page 3 of 20 specifications v dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, rclkin = 6.2 k, 0.5% 50 ppm/c, t min to t max = ?40c to +85c, unless otherwise noted. table 1. parameter value unit test conditions/comments accuracy 1 , 2 measurement error 1 on channel v1 0.1 % reading typ channel v2 with full-scale signal (165 mv), 25c over a dynamic range 500 to 1, line frequency = 45 hz to 65 hz phase error 1 between channels v1 phase lead 37 0.1 degrees max power factor (pf) = 0.8 capacitive v1 phase lag 60 0.1 degrees max pf = 0.5 inductive ac power supply rejection 1 output frequency variation (cf) 0.2 % reading typ s0 = s1 = 1, v1 = 21.2 mv rms, v2 = 116.7 mv rms @ 50 hz, ripple on v dd of 200 mv rms @ 100 hz dc power supply rejection 1 output frequency variation (cf) 0.3 % reading typ s0 = s1 = 1, v1 = 21.2 mv rms, v2 = 116.7 mv rms, v dd = 5 v 250 mv analog inputs 3 channel v1 maximum signal level 30 mv max v1p and v1n to agnd channel v2 maximum signal level 165 mv max v2p and v2n to agnd input impedance (dc) 320 k min osc = 450 khz, rclkin = 6.2 k, 0.5% 50 ppm/c bandwidth (C3 db) 7 khz nominal osc = 450 khz, rclkin = 6.2 k, 0.5% 50 ppm/c adc offset error 1 , 2 18 mv max gain error 1 4 % ideal typ external 2.5 v reference, v1 = 21.2 mv rms, v2 = 116.7 mv rms oscillator frequency (osc) 450 khz nominal rclkin = 6.2 k, 0.5% 50 ppm/c oscillator frequency tolerance 1 12 % reading typ oscillator frequency stability 1 30 ppm/c typ reference input ref in/out input voltage range 2.65 v max 2.45 v nominal 2.25 v min 2.45 v nominal input capacitance 10 pf max on-chip reference 2.45 v nominal reference error 200 mv max temperature coefficient 20 ppm/c typ logic inputs 4 scf, s0, s1 input high voltage, v inh 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 v max v dd = 5 v 5% input current, i in 1 a max typically 10 na, v in = 0 v to v dd input capacitance, c in 10 pf max logic outputs 4 f1 and f2 output high voltage, v oh 4.5 v min i source = 10 ma, v dd = 5 v, i sink = 10 ma, v dd = 5 v output low voltage, v ol 0.5 v max cf output high voltage, v oh 4 v min i source = 5 ma, v dd = 5 v, i sink = 5 ma, v dd = 5 v output low voltage, v ol 0.5 v max frequency output error 1 , 2 (cf) 10 % ideal typ external 2.5 v reference, v1 = 21.2 mv rms, v2 = 116.7 mv rms
ad71056 rev. a | page 4 of 20 parameter value unit test conditions/comments power supply for specified performance v dd 4.75 v min 5 v ? 5% 5.25 v max 5 v + 5% i dd 5 ma max typically 4 ma 1 see the terminology section for an explanation of specifications. 2 see plots in the typical performance characteristics section. 3 see the analog inputs section. 4 sample tested during initial releas e and after any redesign or process change that may affect this parameter. timing characteristics v dd = 5 v 5%, agnd = dgnd = 0 v, on-chip reference, rclkin = 6.2 k, 0.5% 50 ppm/c, t min to t max = ?40c to +85c, unless otherwise noted. sample tested during initial release and after any redesign or process change that may affect this parameter. see figure 2 . table 2. parameter specifications unit test conditions/comments t 1 1 120 ms f1 and f2 pulse width (logic low). t 2 see table 6 sec output pulse period. see the transfer function section. t 3 1/2 t 2 sec time between f1 falling edge and f2 falling edge. t 4 1 , 2 90 ms cf pulse width (logic high). t 5 see table 7 sec cf pulse period. see the transfer function section. t 6 2 s minimum time between f1 and f2 pulses. 1 the pulse widths of f1, f2, and cf ar e not fixed for higher output frequencies. see the frequency outputs section. 2 the cf pulse is always 35 s in high frequency mode. see the frequency outputs section and table 7. timing diagram f1 f2 cf t 1 t 5 t 4 t 2 t 6 t 3 05636-002 figure 2. timing diagram for frequency outputs
ad71056 rev. a | page 5 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to agnd ?0.3 v to +7 v v dd to dgnd ?0.3 v to +7 v analog input voltage to agnd v1p, v1n, v2p, and v2n ?6 v to +6 v reference input voltage to agnd ?0.3 v to v dd + 0.3 v digital input voltage to dgnd ?0.3 v to v dd + 0.3 v digital output voltage to dgnd ?0.3 v to v dd + 0.3 v operating temperature range ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c 16-lead plastic soic, power dissipation 350 mw ja thermal impedance 1 124.9c/w package temperature soldering see j-std-20 1 jedec 1s standard (2-layer) board data. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
ad71056 rev. a | page 6 of 20 terminology measurement error the error associated with the energy measurement made by the ad71056 is defined by the following formula: %100 % ? = energytrue energytrue ad71056 by registered energy error phase error between channels the high-pass filter (hpf) in the current channel (channel v1) has a phase-lead response. to offset this phase response and equalize the phase response between channels, a phase correction network is also placed in channel v1. the phase correction network matches the phase to within 0.1 over a range of 45 hz to 65 hz, and 0.2 over a range 40 hz to 1 khz (see figure 23 and figure 24 ). power supply rejection (psr) this quantifies the ad71056 measurement error as a percentage of reading when the power supplies are varied. for the ac psr measurement, a reading at nominal supplies (5 v) is taken. a 200 mv rms/100 hz signal is then introduced onto the supplies and a second reading is obtained under the same input signal levels. any error introduced is expressed as a percentage of readingsee the measurement error definition. for the dc psr measurement, a reading at nominal supplies (5 v) is taken. the supplies are then varied 5% and a second reading is obtained with the same input signal levels. any error introduced is, again, expressed as a percentage of reading. adc offset error this refers to the small dc signal (offset) associated with the analog inputs to the adcs. however, the hpf in channel v1 eliminates the offset in the circuitry. therefore, the power calculation is not affected by this offset. frequency output error (cf) the frequency output error of the ad71056 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. the difference is expressed as a percentage of the ideal frequency. the ideal frequency is obtained from the ad71056 transfer function. see figure 14 for a typical distribution of part-to-part variation of cf frequency. gain error the gain error of the ad71056 is defined as the difference between the measured output of the adcs (minus the offset) and the ideal output of the adcs. the difference is expressed as a percentage of the ideal output of the adcs. oscillator frequency tolerance the oscillator frequency tolerance of the ad71056 is defined as the part-to-part frequency variation in terms of percentage at room temperature (25c). it is measured by taking the difference between the measured oscillator frequency and the nominal frequency as defined in the specifications section. oscillator frequency stability oscillator frequency stability is defined as the frequency variation in terms of the parts-per-million drift over the operating temperature range. in a metering application, the temperature range is ?40c to +85c. oscillator frequency stability is measured by taking the difference between the measured oscillator frequency at ?40c and +85c and the measured oscillator frequency at +25c.
ad71056 rev. a | page 7 of 20 pin configuration and fu nction descriptions 05636-003 v dd 1 v2p 2 v2n 3 v1n 4 f1 16 f2 15 cf 14 dgnd 13 v1p 5 revp 12 agnd 6 rclkin 11 ref in/out 7 s0 10 scf 8 s1 9 ad71056 top view (not to scale) figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 v dd power supply. this pin provides the supply voltage fo r the circuitry in the ad71056. maintain the supply voltage at 5 v 5% for specified operation. decouple this pin with a 10 f capacitor in parallel with a ceramic 100 nf capacitor. 2, 3 v2p, v2n analog inputs for channel v2 (voltage channel). thes e inputs provide a fully differential input pair. the maximum differential input voltage is 165 mv for sp ecified operation. both inputs have internal esd protection circuitry; an overvoltage of 6 v can be sustained on these inputs without risk of permanent damage. 4, 5 v1n, v1p analog inputs for channel v1 (curre nt channel). these inputs are fully differential voltage inputs with a maximum signal level of 30 mv with respect to th e v1n pin for specified operation. both inputs have internal esd protection circuitry and, in addition, an overvoltage of 6 v can be sustained on these inputs without risk of permanent damage. 6 agnd analog ground. this pin provides the ground reference for the analog circuitry in the ad71056, that is, the adcs and reference. tie this pin to the analog ground plan e of the pcb. the analog ground plane is the ground reference for all analog circuitry, such as antialiasing filters, current and voltage sensors, and so forth. for accurate noise suppression, connect the analog ground plane to the digital ground plane at only one point. a star ground configuration helps to keep noisy di gital currents away from the analog circuits. 7 ref in/out reference voltage. the on-chip reference has a nominal value of 2.45 v and a typical temperature coefficient of 20 ppm/c. an external reference source can also be co nnected at this pin. in eith er case, decouple this pin to agnd with a 1 f tantalum capacitor and a 100 nf ceramic capacitor. the internal reference cannot be used to drive an external load. 8 scf select calibration frequency. this logic input se lects the frequency on the calibration output cf. table 7 shows calibration frequency selections. 9, 10 s1, s0 conversion frequency logic input selection. these logic inputs select one of four possible frequencies for the digital-to-frequency conversion. with this logic input, designers have greater flexibility when designing an energy meter. table 5 shows conversion frequency selections. 11 rclkin on-chip clock enabler. to enable the internal oscillator as a clock source to the chip, a precise low temperature drift resistor at a nominal value of 6. 2 k must be connected from this pin to dgnd. 12 revp negative power indicator. this logic output goes high when negative power is detected, such as when the phase angle between the voltage and current signals is greater than 90. this outp ut is not latched and is reset when positive power is once again detected. the o utput goes high or low at the same time that a pulse is issued on cf. 13 dgnd digital ground. this pin provides the ground reference for the digital circuitry in the ad71056, that is, the multiplier, filters, and digital-to-frequency converter. ti e this pin to the digital ground plane of the pcb. the digital ground plane is the ground reference for all di gital circuitry, for example, counters (mechanical and digital), mcus, and indicator leds. for accurate noise suppression, connect the analog ground plane to the digital ground plane at one point onlya star ground. 14 cf calibration frequency logic output. the cf logic output provides instantaneous real power information. this output is for calibration purposes (also see the scf pin description). 15, 16 f2, f1 low frequency logic outputs. f1 and f2 supply averag e real power information. the logic outputs can be used to directly drive electromechanical counters and 2-phase stepper motors. see the transfer function section.
ad71056 rev. a | page 8 of 20 typical performance characteristics 6.2k ? v2n 200 ? 2 20 v 150nf v2p 200 ? 602k ? v1p v1n 350 ? 40a to 40ma ref in/out 100nf 1f 100nf 10f v dd dgnd f1 f2 cf revp rclkin s0 s1 scf 10nf 10nf 10nf u3 ps2501-1 k7 k8 u1 ad71056 10k ? v dd 200 ? 200 ? 150nf 150nf agnd 150nf v dd + + + 820 ? 2 3 5 4 7 6 13 1 16 15 14 12 11 10 9 8 1 4 2 3 05636-004 figure 4. test circuit for performance curves ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 error (% of reading) 0.2 0.4 0.6 current channe l (% of full scale) 0.1 10 1 100 0.8 1.0 +25c +85c ?40c pf = 1 on-chip reference 05636-005 figure 5. error as a % of reading over temperature with on-chip reference (pf = 1) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 error (% of reading) 0.2 0.4 0.6 current channe l (% of full scale) 0.1 10 1 100 0.8 1.0 +85c, pf = 0.5 ind +25c, pf = 1 ?40c, pf = 0.5 ind +25c, pf = 0.5 ind pf = 0.5 ind on-chip reference 05636-006 figure 6. error as a % of reading over temperature with on-chip reference (pf = 0.5 ind) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 error (% of reading) 0.2 0.4 0.6 current channe l (% of full scale) 0.1 10 1 100 0.8 1.0 +25c +85c ?40c pf = 1 external reference 05636-007 figure 7. error as a % of reading over temperature with external reference (pf = 1) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 error (% of reading) 0.2 0.4 0.6 current channe l (% of full scale) 0.1 10 1 100 0.8 1.0 +85c, pf = 0.5 ind +25c, pf = 1 +25c, pf = 0.5 ind ?40c, pf = 0.5 ind pf = 0.5 ind external reference 05636-008 figure 8. error as a % of reading over temperature with external reference (pf = 0.5 ind)
ad71056 rev. a | page 9 of 20 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 error (% of reading) frequency (hz) 50 45 55 60 65 pf = 0.5 ind pf = 0.5 cap pf = 1 05636-009 figure 9. error as a % of reading over input frequency ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 error (% of reading) 0.2 0.4 0.6 current channe l (% of full scale) 0.1 10 1 100 0.8 1.0 5.25v 5v 4.75v pf = 1 on-chip reference 05636-010 figure 10. psr with on-chip reference, pf = 1 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 error (% of reading) 0.2 0.4 0.6 current channe l (% of full scale) 0.1 10 1 100 0.8 1.0 5.25v 5v 4.75v pf = 1 external reference 05636-011 figure 11. psr with exte rnal reference, pf = 1 40 frequen c y channel v1 offset (mv) ?5?4?3?2?10123456789 external reference temperature = 25c 0 10 20 30 distribution characteristics mean = 2.247828 sds = 1.367176 min = ?2.09932 max = +5.28288 no. of points = 100 05636-012 figure 12. channel v1 offset distribution 0 10 20 30 40 50 frequen c y channel v2 offset (mv) ?12?10?8?6?4?2024681012 external reference temperature = 25c distribution characteristics mean = ?1.563484 sds = 2.040699 min = ?6.82969 max = +2.6119 no. of points = 100 05636-013 figure 13. channel v2 offset distribution ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 0 200 400 600 800 1000 frequen c y deviation from mean (%) external reference temperature = 25c distribution characteristics mean = 0% sds = 1.55% min = ?11.79% max = +6.08% no. of points = 3387 05636-014 figure 14. part-to-part cf distribution from mean of cf
ad71056 rev. a | page 10 of 20 theory of operation the two adcs in the ad71056 digitize the voltage signals from the current and voltage sensors. these adcs are 16-bit, - with an oversampling rate of 450 khz. this analog input struc- ture greatly simplifies sensor interfacing by providing a wide dynamic range for direct connection to the sensor and also simplifies the antialiasing filter design. a high-pass filter in the current channel removes any dc component from the current signal. this eliminates any inaccuracies in the real power calculation due to offsets in the voltage or current signals. the real power calculation is derived from the instantaneous power signal. the instantaneous power signal is generated by a direct multiplication of the current and voltage signals. to extract the real power component (that is, the dc component), the instantaneous power signal is low-pass filtered. figure 15 illustrates the instantaneous real power signal and shows how the real power information is extracted by low-pass filtering the instantaneous power signal. this scheme correctly calculates real power for sinusoidal current and voltage waveforms at all power factors. all signal processing is carried out in the digital domain for superior stability over temperature and time. time time adc adc c h1 c h2 multiplier f1 f2 digital-to- frequency cf digital-to- frequency instantaneous real power signal instantaneous power signal ? p(t) lpf hpf 05636-015 figure 15. signal processing block diagram the low frequency outputs (f1, f2) of the ad71056 are generated by accumulating this real power information. this low frequency inherently means a long accumulation time between output pulses. consequently, the resulting output frequency is proportional to the average real power. this average real power information is then accumulated (for example, by a counter) to generate real energy information. conversely, due to its high output frequency and, hence, shorter integration time, the cf output frequency is proportional to the instantaneous real power. this is useful for system calibration that can be done faster under steady load conditions. power factor considerations the method used to extract the real power information from the instantaneous power signal (that is, by low-pass filtering) is valid even when the voltage and current signals are not in phase. figure 16 displays the unity power factor condition and a displacement power factor (dpf) = 0.5; that is, the current signal lagging the voltage by 60. assuming the voltage and current waveforms are sinusoidal, the real power component of the instantaneous power signal (the dc term) is given by ( ? ? ? ? ? ? iv ) (1) this is the correct real power calculation. v i 2 0v power current and voltage power time time voltage current v i 2 cos (60) 0v in s t a nt a neous power signal in s tantaneous real power signal instantaneous power signal instantaneous real power signal 60 05636-016 figure 16. dc component of instantaneous power signal conveys real power information, pf < 1 nonsinusoidal voltage and current the real power calculation method also holds true for non- sinusoidal current and voltage waveforms. all voltage and current waveforms in practical applications have some harmonic content. using the fourier transform, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content. ( h 0h h 0 thv vtv ++= ) (2) where: v(t) is the instantaneous voltage. v 0 is the average value. v h is the rms value of voltage harmonic h. i s the phase angle of the voltage harmonic. h
ad71056 rev. a | page 11 of 20 ( +?+= oh h th h i 0 iti sin 2)( ) (3) where: i(t) is the instantaneous current. i 0 is the dc component. i h is the rms value of current harmonic h. h is the phase angle of the current harmonic. using equation 2 and equation 3, the real power, p, can be expressed in terms of its fundamental real power (p 1 ) and harmonic real power (p h ) as p = p 1 + p h where: p 1 = v 1 i 1 cos ? 1 (4) ? 1 = 1 ? 1 and p h = 1h h h vp i h cos ? h (5) ? h = h ? h in equation 5, a harmonic real power component is generated for every harmonic, provided that harmonic is present in both the voltage and current waveforms. the power factor calculation has previously been shown to be accurate in the case of a pure sinusoid. therefore, the harmonic real power must also correctly account for the power factor because it is made up of a series of pure sinusoids. note that the input bandwidth of the analog inputs is 7 khz at the nominal internal oscillator frequency of 450 khz.
ad71056 rev. a | page 12 of 20 applications analog inputs channel v1 (current channel) the voltage output from the current sensor is connected to the ad71056 at channel v1. channel v1 is a fully differential voltage input. v1p is the positive input with respect to v1n. the maximum peak differential signal on channel v1 should be less than 30 mv (21 mv rms for a pure sinusoidal signal) for specified operation. +30mv ?30mv v cm v 1 differential input 30mv max peak common mode 6.25mv max v1p v1n v1 v cm agnd 05636-017 figure 17. maximum signal levels, channel v1 figure 17 illustrates the maximum signal levels on v1p and v1n. the maximum differential voltage is 30 mv. the differential voltage signal on the inputs must be referenced to a common mode, such as agnd. the maximum common-mode signal is 6.25 mv, as shown in figure 17. channel v2 (voltage channel) the output of the line voltage sensor is connected to the ad71056 at channel v2. channel v2 is a fully differential voltage input with a maximum peak differential signal of 165 mv. figure 18 illustrates the maximum signal levels that can be connected to the ad71056 channel v2. +165m v ? 165mv v cm v 2 differential input 165mv max peak common mode 25mv max v2p v2n v2 v cm agnd 05636-018 figure 18. maximum signal levels, channel v2 channel v2 is usually driven from a common-mode voltage, that is, the differential voltage signal on the input is referenced to a common mode (usually agnd). the analog inputs of the ad71056 can be driven with common-mode voltages of up to 25 mv with respect to agnd. however, best results are achieved using a common mode equal to agnd. typical connection diagrams figure 19 shows a typical connection diagram for channel v1. a shunt is the current sensor selected for this example because of its low cost compared to other current sensors, such as the current transformer (ct). this ic is ideal for low current meters. v 1p v1n c f c f r f r f 30mv shunt agnd phase neutral 05636-019 figure 19. typical connection for channel v1 figure 20 shows a typical connection for channel v2. typically, the ad71056 is biased around the phase wire and a resistor divider is used to provide a voltage signal that is proportional to the line voltage. adjusting the ratio of r a , r b , and r f is also a convenient way of carrying out a gain calibration on a meter. v2p v2n c f phase neutral r f 165mv c f r f r b r a 1 1 r a >> r b + r f . 05636-020 figure 20. typical connections for channel v2
ad71056 rev. a | page 13 of 20 power supply monitor the ad71056 contains an on-chip power supply monitor. the power supply (v dd ) is continuously monitored by the ad71056. if the supply is less than 4 v, the ad71056 becomes inactive. this is useful to ensure proper device operation at power-up and power-down. the power supply monitor has built-in hysteresis and filtering that provide a high degree of immunity to false triggering from noisy supplies. in figure 21 , the trigger level is nominally set at 4 v. the tolerance on this trigger level is within 5%. the power supply and decoupling for the part should be such that the ripple at v dd does not exceed 5 v 5% as specified for normal operation. v dd 5v 4v 0v time inactive active inactive internal a ctivation 05636-021 figure 21. on-chip power supply monitor hpf and offset effects figure 22 illustrates the effect of offsets on the real power calculation. as can be seen, offsets on channel v1 and channel v2 contribute a dc component after multiplication. because this dc component is extracted by the lpf and used to generate the real power information, the offsets contribute a constant error to the real power calculation. this problem is easily avoided by the built-in hpf in channel v1. by removing the offsets from at least one channel, no error component can be generated at dc by the multiplication. error terms at the line frequency () are removed by the lpf and the digital-to- frequency conversion (see the digital-to-frequency conversion section). dc component (including error term) is extracted by the lpf for real power calculation i os v v os i v os i os v i 2 0 frequency (rad/s) 05636-022 figure 22. effect of channel offset on the real power calculation equation 6 shows how the power calculation is affected by the dc offsets in the current and voltage channels. ( ) { } ( ) { } + + cos cos (6) () () ?+?++ = cos cos 2 () ? + 2cos 2 the hpf in channel v1 has an associated phase response that is compensated for on chip. figure 23 and figure 24 show the phase error between channels with the compensation network activated. the ad71056 is phase compensated up to 1 khz as shown. this ensures correct active harmonic power calculation even at low power factors. frequency (hz) 0.30 phase (degrees) 0.25 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 0 100 200 300 400 500 600 700 800 900 1000 05636-023 figure 23. phase error between channels (0 hz to 1 khz) frequency (hz) 0.30 phase (degrees) 0.25 0.20 0.15 0.10 0.05 0 ? 0.05 ? 0.10 40 45 50 55 60 65 70 05636-024 figure 24. phase error between channels (40 hz to 70 hz)
ad71056 rev. a | page 14 of 20 digital-to-frequency conversion as previously described, the digital output of the low-pass filter after multiplication contains the real power information. however, because this lpf is not an ideal brick wall filter implementation, the output signal also contains attenuated components at the line frequency and its harmonicsthat is, cos(ht), where h = 1, 2, 3, . . . and so on. the magnitude response of the filter is given by () 2 2 45.4 1 1 f fh + = (7) for a line frequency of 50 hz, this gives an attenuation of the 2 (100 hz) component of approximately 22 db. the dominating harmonic is twice the line frequency (2) due to the instantaneous power calculation. figure 25 shows the instantaneous real power signal at the output of the lpf that still contains a significant amount of instantaneous power information, that is, cos(2t). this signal is then passed to the digital-to-frequency converter where it is integrated (accumulated) over time to produce an output frequency. the accumulation of the signal suppresses or averages out any non-dc components in the instantaneous real power signal. the average value of a sinusoidal signal is zero. thus, the frequency generated by the ad71056 is proportional to the average real power. figure 25 shows the digital-to- frequency conversion for steady load conditions, that is, constant voltage and current. f1 f2 digital-to- frequency cf digital-to- frequency multiplier f1 time cf time frequency frequency v i 0 frequency (rad/s) & 2 & cos (2 & ) attenuated by lpf vi 2 lpf to extract real power (dc term) instantaneous real power signal (frequency domain) lpf 05636-025 figure 25. real power-to-frequency conversion figure 25 shows that the frequency output cf varies over time, even under steady load conditions. this frequency variation is primarily due to the cos(2t) component in the instantaneous real power signal. the output frequency on cf can be up to 2048 times higher than the frequency on f1 and f2. this higher output frequency is generated by accumulating the instantaneous real power signal over a much shorter time while converting it to a frequency. this shorter accumulation period means less averaging of the cos(2t) component. consequently, some of this instantaneous power signal passes through the digital-to-frequency conversion. this is not a problem in the application. where cf is used for calibration purposes, the frequency should be averaged by the frequency counter to remove any ripple. if cf is being used to measure energy, for example in a microprocessor-based application, the cf output should also be averaged to calculate power. because the f1 and f2 outputs operate at a much lower frequency, a lot more averaging of the instantaneous real power signal is carried out. the result is a greatly attenuated sinusoidal content and a virtually ripple free frequency output. connecting to a microcontroller for energy measurement the easiest way to interface the ad71056 to a microcontroller is to use the cf high frequency output with the output frequency scaling set to 2048 f1, f2. this is done by setting scf = 0 and s0 = s1 = 1 (see table 7 ). with full-scale ac signals on the analog inputs, the output frequency on cf is approximately 2.867 khz. figure 26 illustrates one scheme to digitize the output frequency and carry out the necessary averaging mentioned in the digital- to-frequency conversion section. cf time 10% frequency ripple average frequency ad71056 counter timer mcu cf 05636-026 figure 26. interfacing the ad71056 to an mcu as shown, the frequency output cf is connected to an mcu counter or port. this counts the number of pulses in a given integration time that is determined by an mcu internal timer. the average power proportional to the average frequency is given by time counter power average frequency average = = (8)
ad71056 rev. a | page 15 of 20 the energy consumed during an integration period is given by counter time time counter time power average energy = = = (9) for the purpose of calibration, this integration time can be as long as 10 seconds to 20 seconds to accumulate enough pulses to ensure correct averaging of the frequency. in normal operation, the integration time can be reduced to one or two seconds, depending, for example, on the required update rate of a display. with shorter integration times on the mcu, the amount of energy in each update can still have some small amount of ripple, even under steady load conditions. however, over a minute or more the measured energy has no ripple. power measurement considerations calculating and displaying power information always has some associated ripple that depends on the load as well as the integration period used in the mcu to determine average power. for example, at light loads, the output frequency may be 10 hz. with an integration period of two seconds, only about 20 pulses are counted. the possibility of missing one pulse always exists, because the output frequency of the ad71056 is running asynchronously to the mcu timer. this results in a 1-in-20, or 5%, error in the power measurement. internal oscillator (osc) the nominal internal oscillator frequency is 450 khz when used with rclkin, with a nominal value of 6.2 k. the frequency outputs are directly proportional to the oscillator frequency, thus rclkin must have low tolerance and low temperature drift to ensure stability and linearity of the chip. the oscillator frequency is inversely proportional to the rclkin, as shown in figure 27. although the internal oscillator operates when used with rclkin values between 5.5 k and 20 k, choosing a value within the range of the nominal value, as shown in figure 27, is recommended. resistance (k ? ) 5.8 5.9 6.1 6.3 6.7 frequen c y (khz) 420 430 440 450 460 480 470 490 6.0 6.2 6.4 6.5 6.6 410 400 05636-027 figure 27. effect of rclkin on internal oscillator frequency (osc) transfer function frequency outputs f1 and f2 the ad71056 calculates the product of two voltage signals (on channel v1 and channel v2) and then low-pass filters this product to extract real power information. this real power information is then converted to a frequency. the frequency information is output on f1 and f2 in the form of active low pulses. the pulse rate at these outputs is relatively low, for example, 0.175 hz maximum for ac signals with s0 = s1 = 0 (see table 6). this means that the frequency at these outputs is generated from real power information accumulated over a relatively long period of time. the result is an output frequency that is proportional to the average real power. the averaging of the real power signal is implicit to the digital-to-frequency conversion. the output frequency or pulse rate is related to the input voltage signals by the following equation: 2 ... 75 . 494 ref 4 1 rms rms v f v2 v1 freq = (10) where: freq = output frequency on f1 and f2 (hz). v1 rms = differential rms voltage signal on channel v1 (v). v2 rms = differential rms voltage signal on channel v2 (v). v ref = the reference voltage (2.45 v 200 mv) (v). f 14 = one of four possible frequencies selected by using logic input s0 and logic input s1 (see table 5). table 5. f 14 frequency selection s1 s0 osc relation 1 f 1 4 at nominal osc (hz) 2 0 0 osc/2 19 0.86 0 1 osc/2 18 1.72 1 0 osc/2 17 3.43 1 1 osc/2 16 6.86 1 f 14 is a binary fraction of the internal oscillator frequency (osc). 2 values are generated using the nominal frequency of 450 khz. example in this example, with ac voltages of 30 mv peak applied to v1 and 165 mv peak applied to v2, the expected output frequency is calculated as f 14 = osc/2 19 hz, s0 = s1 = 0 v1 rms = 0.03/2 v v2 rms = 0.165/2 v v ref = 2.45 v (nominal reference value) note that if the on-chip reference is used, actual output frequencies can vary from device to device due to the reference tolerance of 200 mv. 175 . 0 204 . 0 45 . 2 2 2 165 . 0 03 . 0 75 . 494 2 = = = 1 1 f f freq (11)
ad71056 rev. a | page 16 of 20 table 6. maximum output frequency on the f1 and f2 pins s1 s0 osc relation max frequency 1 or ac inputs (hz) 0 0 0.204 f 1 0.175 0 1 0.204 f 2 0.35 1 0 0.204 f 3 0.70 1 1 0.204 f 4 1.40 1 values are generated using the nominal frequency of 450 khz. frequency output cf the pulse output cf (calibration frequency) is intended for calibration purposes. the output pulse rate on cf can be up to 2048 times the pulse rate on the f1 and f2 pins. the lower the f 14 frequency selected, the higher the cf scaling (except for the high frequency mode where scf = 0, s1 = s0 = 1). tabl e 7 shows how the two frequencies are related, depending on the states of the logic inputs (s0, s1, and scf). due to its relatively high pulse rate, the frequency at the cf logic output is proportional to the instantaneous real power. as with f1 and f2, cf is derived from the output of the low-pass filter after multiplication. however, because the output frequency is high, this real power information is accumulated over a much shorter time. therefore, less averaging is carried out in the digital-to- frequency conversion. with much less averaging of the real power signal, the cf output is much more responsive to power fluctuations (see the signal processing block in figure 15 ). table 7. maximum output frequency on cf scf s1 s0 cf max for ac signals (hz) 1 1 0 0 128 f1, f2 = 22.4 0 0 0 64 f1, f2 = 11.2 1 0 1 64 f1, f2 = 22.4 0 0 1 32 f1, f2 = 11.2 1 1 0 32 f1, f2 = 22.4 0 1 0 16 f1, f2 = 11.2 1 1 1 16 f1, f2 = 22.4 0 1 1 2048 f1, f2 = 2.867 khz 1 values are generated using the nominal frequency of 450 khz. selecting a frequency for an energy meter application as listed in table 5 , the user can select one of four frequencies. this frequency selection determines the maximum frequency on the f1 and f2 pins. these outputs are intended for driving an energy register (electromechanical or other). because only four different output frequencies can be selected, the available frequency selection is optimized for a meter constant of 100 imp/kwh with a maximum current between 10 a and 120 a. table 8 shows the output frequency for several maxi- mum currents (i max ) with a line voltage of 220 v. in all cases, the meter constant is 100 imp/kwh. table 8. f1 and f2 frequency at 100 imp/kwh i max (a) f1 and f2 (hz) 12.5 0.076 25.0 0.153 40.0 0.244 60.0 0.367 80.0 0.489 120.0 0.733 the f 14 frequencies allow complete coverage of this range of output frequencies (f1, f2). when designing an energy meter, the nominal design voltage on channel v2 (voltage) should be set to half-scale to allow for calibration of the meter constant. the current channel should also be no more than half-scale when the meter sees maximum load. this allows overcurrent signals and signals with high crest factors to be accommodated. table 9 lists the output frequency on the f1 and f2 pins when both analog inputs are half-scale. the frequencies listed in table 9 align very well with those listed in table 8 for maximum load. table 9. f1 and f2 frequency with half-scale ac inputs s1 s0 f 14 (hz) frequency on f1 and f2 ch1 and ch2 half-scale ac input 1 0 0 0.86 0.051 f 1 0.044 hz 0 1 1.72 0.051 f 2 0.088 hz 1 0 3.43 0.051 f 3 0.176 hz 1 1 6.86 0.051 f 4 0.352 hz 1 values are generated using the nominal frequency of 450 khz. when selecting a suitable f 14 frequency for a meter design, compare the frequency output at i max (maximum load) based on a meter constant of 100 imp/kwh against the last column of table 9 . the closest frequency in table 9 determines the best choice of frequency ( f 14 ). for example, if a meter with a maximum current of 25 a is being designed, the output frequency on the f1 and f2 pins with a meter constant of 100 imp/kwh is 0.153 hz at 25 a and 220 v (from table 8 ). in the last column of tabl e 9 , the closest frequency to 0.153 hz is 0.176 hz. therefore, f 3 (3.43 hz) is selected for this design (see table 5 ). frequency outputs figure 2 shows a timing diagram for the various frequency outputs. the outputs (f1 and f2) are the low frequency outputs that can be used to directly drive a stepper motor or electro- mechanical impulse counter. the f1 and f2 outputs provide two alternating low frequency pulses. the f1 and f2 pulse widths (t 1 ) are set such that if they fall below 240 ms (0.24 hz), they are set to half of their period. the maximum output frequencies for f1 and f2 are shown in table 6 . the high frequency cf output is intended to be used for communications and calibration purposes. cf produces a 90-ms-wide active high pulse (t 4 ) at a frequency proportional
ad71056 rev. a | page 17 of 20 to active power. the cf output frequencies are given in table 7 . as with f1 and f2, if the period of cf (t 5 ) falls below 180 ms, the cf pulse width is set to half the period. if the cf frequency, for example, is 20 hz, the cf pulse width is 25 ms. when the high frequency mode is selected (that is, scf = 0, s1 = s0 = 1), the cf pulse width is fixed at 35 s. therefore, t 4 is always 35 s, regardless of the output frequency on cf. no load threshold the ad71056 also includes a no load threshold and start-up current feature that eliminates any creep effects in the meter. the ad71056 is designed to issue a minimum output frequency. any load generating a frequency lower than this minimum frequency does not cause a pulse to be issued on f1, f2, or cf. the minimum output frequency is given as 0.00244% for each of the f 14 frequency selections (see table 5 ). for example, for an energy meter with a meter constant of 100 imp/kwh on f1, f2 using f 3 (3.43 hz), the minimum output frequency at f1 or f2 equals 0.00244% of 3.43 hz or 8.38 10 C5 hz. this is 2.68 10 C3 hz at cf (32 f1 hz) when scf = s0 = 1, s1 = 0. in this example, the no load threshold is equivalent to 3 w of load or a start-up current of 13.72 ma at 220 v. compare this value to the iec62053-21 specification that states the meter must start up with a load equal to or less than 0.4% ib. for a 5 a (ib) meter, 0.4% of ib is equivalent to 20 ma. negative power information the ad71056 detects when the current and voltage channels have a phase shift greater than 90. this mechanism can detect wrong connection of the meter or generation of negative power. the revp pin output goes active high when negative power is detected and active low when positive power is detected. the revp pin output changes state as a pulse is issued on cf.
ad71056 rev. a | page 18 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ac 10.00 (0.3937) 9.80 (0.3858) 16 9 8 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 060606-a 45 figure 28. 16-lead standard small outline package [soic_n] narrow body (r-16) dimensions shown in millimeters and (inches) ordering guide model temperature range package description package option ad71056ar ?40c to +85c 16-lead soic_n r-16 ad71056ar-rl ?40c to +85c 16-lead soic_n, reel r-16 ad71056arz 1 ?40c to +85c 16-lead soic_n r-16 ad71056arz-rl 1 ?40c to +85c 16-lead soic_n, reel r-16 1 z = pb-free part.
ad71056 rev. a | page 19 of 20 notes
ad71056 rev. a | page 20 of 20 notes ?2006 a nalog d evices, i nc. a ll r ights r eserved. t rademarks a nd r egistered t rademarks a re t he p roperty o f t heir r espective o wners. d05636-0-8/06(a)

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